Sandblaster® ISA

From the start, Optimum Semiconductor set off to define a wireless platform that would offer revolutionary capability to handset manufacturers, with the following goals:

• Efficiently implement a wide range of advanced communications protocols and multimedia applications
• Allow simultaneous execution of computationally intensive tasks in real-time
• Provide for a high degree of flexibility and re-use of silicon
• Offer a programming environment that is substantially more
  efficient than traditional DSP programming

To achieve those goals while preserving low power appropriate for handset designs requires employing new techniques at every level of design – architecture and micro architecture, logic and circuit design, plus algorithm and software design. The result is the Sandblaster® Instruction Set Architecture (ISA).

The Sandblaster® Instruction Set Architecture (ISA)

The Sandblaster® ISA employs a number of architectural advancements that deliver a quantum leap in raw DSP performance along with a system design that allows the handset developer to implement real-world communications systems and devices. In the multi-threaded Sandblaster® design, eight (8) hardware threads operate simultaneously – and the software system enables near-limitless software parallelism without the traditional performance penalties associated with task switching. Rather than imposing a cumbersome development or design process on the development team, Optimum Semiconductor provides a standard C language compiler that can directly emit high performance code that does not require assembly language programming or intrinsics. The Sandblaster® architecture also includes a SIMD/Vector DSP unit, a parallel reduction unit, a RISC-based integer unit, and instruction set support for Java execution.

In total, the architectural innovations each contribute to making the Sandblaster® the most powerful, energy efficient
C-compliable DSP in the world.